This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-295234, filed Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) for use in electronic equipment driven by a battery of, for example, a mobile terminal unit.
2. Description of the Related Art
With an improvement in micro-lithographic processes and a decrease in supply voltage of an IC, the threshold voltage of transistors thereof has been lowered. A reduced threshold voltage enhances the operating speed of the transistors. A decrease in threshold voltage, on the other hand, brings about an increase in leakage current of the transistors in a standby state, a major problem.
Electronic equipment driven by a battery of a mobile terminal unit, in particular, needs to prolong the standby time as much as possible. Accordingly, it is important for an LSI installed in this kind of electronic equipment to have a reduced standby current. To reduce the standby current, there has been employed such a method that uses, for example, an MT (Multi-Threshold)-CMOS or turns OFF the power supply in the standby state, thus suppressing a current flowing through the LSI when it is not operating.
FIG. 13 shows one example of the above-mentioned MT-CMOS circuit. This MT-CMOS circuit is constituted of a low-threshold voltage circuit block 1, a P-channel MOS transistor Q1 having an ordinary threshold voltage, and an N-channel MOS transistor Q2. The low-threshold voltage circuit block 1 is connected between a virtual power supply line VDD1 and a virtual ground line VSS1. This low-threshold voltage circuit block 1 includes a plurality of transistors having a threshold voltage lower than those of the transistors Q1 and Q2. That is, this low-threshold voltage circuit block 1 includes a cell constituted of a plurality of logic circuits not shown. The transistor Q1 is connected between the virtual power supply line VDD1 and a power supply line VDD and the transistor Q2, between the virtual ground line VSS1 and the ground line VSS. Those transistors Q1 and Q2 are controlled by a control signal E.
In an active state (operating state), when the control signal E is activated, the transistors Q1 and Q2 are turned ON. This causes a supply voltage to be fed to the low-threshold voltage circuit block 1 through the transistors Q1 and Q2. The low-threshold voltage circuit block 1 operates at a high speed because it is made up of the low-threshold voltage transistors.
Furthermore, in a standby state, when the control signal E is deactivated, the transistors Q1 and Q2 are turned OFF. This causes a path interconnecting the power supply line and the ground line VSS to be interrupted, thus inhibiting a leakage current from occurring.
In the MT-CMOS circuit shown in FIG. 13, the transistors Q1 and Q2 act to control supply of power fed to all over the low-threshold voltage circuit block 1. A contrastive configuration may be possible in which only the cell of part of the logic circuit is made up of low-threshold voltage transistors.
In FIG. 14, a gate circuit 2 includes a logic circuit, indicated by a hatched line, which constitutes a critical path, for example. Before and behind the gate circuit 2 is connected a plurality of flip-flop circuits. Of these flip-flop circuits such flip-flop circuits (which are indicated by a hatched line) that are connected to the logic circuit of the above-mentioned critical path are made up of low-threshold voltage transistors in configuration. Such a configuration enables reducing the number of transistors with a low threshold voltage. This in turn enables reducing a leakage current in the standby state, thus leading to a high-speed operation.
The leakage current, however, flows not only when the semiconductor chip or the gate circuit is stopped but also when it is operating. With a recent trend for a lower power dissipation of the semiconductor IC, the leakage current in the operating state has been occupying a non-negligible proportion with respect to the original operating current dissipation.
In the circuit shown in FIGS. 13 and 14, however, in the active state, a leakage current flows through the low-threshold voltage transistors. To reduce the leakage current in the active state there is only one method available of enhancing the threshold voltage of the transistors. This method of enhancing the threshold voltage, however, is not desirable because the circuit is degraded in operating speed. Accordingly, this is desired such a semiconductor circuit that can reduce the leakage current even in the active state.
According to an aspect of the present invention, there is provided a semiconductor IC comprising: a combination circuit to which an I/O signal and a control signal are supplied and which is switched between an active state where power is supplied according to the control signal and an inactive state where the power is interrupted; and flip-flop circuits which have input terminals connected to the output terminals of the combination circuit and which store an output signal of the combination circuit according to the clock signal, wherein the combination circuit is set to an operating state by the control signal immediately before the flip-flop circuits start to operate.